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3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module 168 pin unbuffered COB-DIMM Modules
HYS64/72V2200GCU-10 HYS64/72V4220GCU-10
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168 Pin unbuffered 8 Byte Dual-In-Line SDRAM Modules in COB (" hip-on-Board" techniques C ) for PC main memory applications 1 bank 2M x 64, 2M x 72 and 2 bank 4M x 64, 4M x 72 organisation Optimized for byte-write non-parity or ECC applications JEDEC standard Synchronous DRAMs (SDRAM) Fully PC board layout compatible to INTEL' Rev. 1.0 module specification s Performance:
-10 fCK tAC Max. Clock frequency Max. access time from clock 66 MHz @ CL=2 100 MHz @ CL=3 9 ns @ CL=2 8 ns @ CL=3
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Single +3.3V( 0.3V ) power supply Programmable CAS Latency, Burst Length and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh Decoupling capacitors mounted on substrate All inputs, outputs are LVTTL compatible Serial Presence Detect with E 2PROM Utilizes 2M x 8 SDRAMs dies in Chip-on-Board technique 4096 refresh cycles every 64 ms Gold contact pad Card Size: 133,35 mm x 25,40 mm x 4,00 mm
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Semiconductor Group
1
2.98
HYS64(72)V2200/4220GCU-10 SDRAM-Modules
The HYS64(72)2200GCU and HYS64(72)4220GCU are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs) which are organised as 2M x 64, 2M x 72 in 1 bank and 4M x 64 and 4M x 72 in two banks high speed memory arrays designed with Synchronous DRAMs (SDRAMs) for non-parity and ECC applications. Decoupling capacitors are mounted on the PC board. The PC board design is according to INTEL' PC SDRAM s unbuffered DIMM specification and the SDRAM dies are assebled in COB technique. The DIMMs have a serial presence detect, implemented with a serial E 2PROM using the two pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All SIEMENS 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133,35 mm long footprint, with 1"( 25,40 mm) height.
Ordering Information
Type HYS 64V2200GCU--10 HYS 72V2200GCU-10 HYS 64V4220GCU-10 HYS 72V4220GCU-10 Ordering Code Package L-DIM-168-C2 L-DIM-168-C2 L-DIM-168-C2 L-DIM-168-C2 Descriptions
66 Mhz 2M x 64 1 bank COB-SDRAM module 66 MHz 2M x 72 1 bank COB-SDRAM module 66 Mhz 4M x 64 2 bank COB-SDRAM module 66 Mhz 4M x 72 2 bank COB-SDRAM module
Module Height 1" 1" 1" 1"
Pin Names
A0-A10 BA DQ0 - DQ63 CB0-CB7 RAS CAS WE CKE0, CKE1 CLK0 - CLK3 DQMB0 - DQMB7 CS0 - CS3 Vcc Vss SCL SDA N.C. Address Inputs( RA0 ~ RA10 / CA0 ~ CA8) Bank Address Data Input/Output Check Bits (x72 organisation only) Row Address Strobe Column Address Strobe Read / Write Input Clock Enable Clock Input Data Mask Chip Select Power (+3.3 Volt) Ground Clock for Presence Detect Serial Data Out for Presence Detect No Connection
Address Format:
2M x 64 2M x 72 4M x 64 4M x 72 Part Number HYS64V2200GCU HYS72V2200GCU HYS64V4220GCU HYS72V4220GCU Rows 11 11 11 11 Columns 9 9 9 9 Banks 1 1 1 1 Refresh 4k 4k 4k 4k Period 64 ms 64 ms 64 ms 64 ms Interval 15,6 s 15,6 s 15,6 s 15,6 s
Semiconductor Group
2
HYS64(72)V2200/4220GCU-10 SDRAM-Modules
Pin Configuration
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Symbol VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 NC (CB0) NC (CB1) VSS NC NC VCC WE DQMB0 DQMB1 CS0 DU VSS A0 A2 A4 A6 A8 A10 NC VCC VCC CLK0 PIN # 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Symbol VSS DU CS2 DQMB2 DQMB3 DU VCC NC NC NC (CB2) NC (CB3) VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC DU CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC WP SDA SCL VCC PIN # 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Symbol VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 NC (CB4) NC (CB5) VSS NC NC VCC CAS DQMB4 DQMB5 CS1 RAS VSS A1 A3 A5 A7 A9 BA NC VCC CLK1 NC PIN # 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Symbol VSS CKE0 CS3 DQMB6 DQMB7 NC VCC NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 NC DU NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC SA0 SA1 SA2 VCC
Note : Pinnames in brackets are for the x72 ECC versions
Semiconductor Group
3
HYS64(72)V2200/4220GCU-10 SDRAM-Modules
WE CS0 DQMB0 DQ(7:0) CS WE DQM DQ0-DQ7 D0 CS WE DQMB1 DQ(15:8) DQM DQ0-DQ7 D1 CS WE DQM CB(7:0) CS2 DQMB2 DQ(23:16) CS WE DQM DQ0-DQ7 D2 CS WE DQMB3 DQ(31:24) DQM DQ0-DQ7 D3 D0 - D7,(D8) D0 - D7,(D8) C0-C7,(C8) VSS RAS CAS CKE0 D0 - D7,(D8) D0 - D7,(D8) D0 - D7,(D8) CLK0 CLK1 CLK2 CLK3 Clock Wiring 2M x 64 2M x 72 4 SDRAM+3.3pF 5 SDRAM Termination Termination 4 SDRAM+3.3pF 4 SDRAM+3.3pF Termination Termination D0 - D7,(D8) E2PROM (256wordx8bit) SA0 SA1 SA2 SCL SA0 SA1 SA2 SCL DQMB7 DQ(63:56) DQM DQ0-DQ7 D7 DQMB6 DQ(55:48) DQM DQ0-DQ7 D6 CS WE CS WE DQ0-DQ7 D8 DQMB5 DQ(47:40) DQM DQ0-DQ7 D5 DQMB4 DQ(39:32) DQM DQ0-DQ7 D4 CS WE CS WE
A0-A10,BA VCC
SDA WP 47k
Note: D8 is only used in the x72 ECC version
Block Diagram for 2M x 64/72 SDRAM DIMM modules (HYS64/72V2200GCU) Semiconductor Group 4
HYS64(72)V2200/4220GCU-10 SDRAM-Modules
CS1 CS0 CS DQMB0 DQ(7:0) DQM DQ0-DQ7 D0 CS DQMB1 DQ(15:8) DQM DQM DQM DQ0-DQ7 D8 CS DQMB5 DQ(47:40) DQM CS DQMB4 DQ(39:32) DQM DQ0-DQ7 D4 CS DQM CS DQM DQ0-DQ7 D12 CS CS
DQ0-DQ7 DQ0-DQ7 D1 D9 CS DQM DQ0-DQ7 D16 CS DQM DQ0-DQ7 D17
DQ0-DQ7 DQ0-DQ7 D5 D13
CB(7:0) CS3 CS2
CS DQMB2 DQ(23:16) DQM DQ0-DQ7 D2 CS DQMB3 DQ(31:24) DQM DQ0-DQ7 D3 DQM DQM
CS DQMB6 DQ(55:48) DQM DQ0-DQ7 D10 CS DQMB7 DQ(63:56) DQM DQ0-DQ7 D11
CS DQM DQ0-DQ7 D6 CS DQM DQ0-DQ7 D7
CS DQ0-DQ7 D14 CS DQ0-DQ7 D15
A0-A10,BA VDD VSS
D0 - D15,(D16,D17) D0 - D15,(D16,D17) C0-C31,(C32..C35) D0 - D7,(D8) D0 - D15,(D16,D17) D0 - D7,(D16)
VDD
E2PROM (256wordx8bit) SA0 SA1 SA2 SCL SA0 SA1 SA2 SCL SDA WP 47k
RAS, CAS, WE CKE0 10k CKE1
D9 - D15,(D17)
CLK0 CLK1 CLK2 CLK3
Clock Wiring 4M x 64 4M x 72 4 SDRAM+3.3pF 5 SDRAM 4 SDRAM+3.3pF 5 SDRAM 4 SDRAM+3.3pF 4 SDRAM+3.3pF 4 SDRAM+3.3pF 4 SDRAM+3.3pF
Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10 Ohms except otherwise noted.
Block Diagram for 4M x 64/72 SDRAM DIMM modules (HYS64/72V4220GCU) Semiconductor Group 5
HYS64(72)V2200/4220GCU-10 SDRAM-Modules
DC Characteristics TA = 0 to 70 C; VSS = 0 V; VDD,VDDQ = 3.3 V 0.3 V Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 2.0 mA) Output low voltage (IOUT = 2.0 mA) Input leakage current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) Output leakage current (DQ is disabled, 0 V < VOUT < VCC) Symbol Limit Values min. max. Vcc+0.3 0.8 - 0.4 40 40 V V V V A A 2.0 - 0.5 2.4 - - 40 - 40 Unit
VIH VIL VOH VOL II(L) IO(L)
Capacitance TA = 0 to 70 C; VDD = 3.3 V 0.3 V, f = 1 MHz Parameter Symbol Limit Values max. max. max. max. 2Mx64 2Mx72 4Mx64 4Mx72 Input capacitance
(A0 to A10, BA, RAS, CAS, WE)
Unit
CI1 CI2 CICL CI3 CI4 CIO
Csc Csd
45 20 22 22 13 13 8 10
55 25 38 38 13 12 8 10
80 30 22 50 20 20 8 10
90 35 38 55 20 20 8 10
pF pF pF pF pF pF pF pF
Input capacitance (CS0 -CS3 ) Input capacitance (CLK0 - CLK3) Input capacitance (CKE0, CKE1) Input capacitance (DQMB0 - DQMB7) Input / Output capacitance
(DQ0-DQ63,CB0-CB7)
Input Capacitance (SCL,SA0-2) Input/Output Capacitance
Semiconductor Group
6
HYS64(72)V2200/4220GCU-10 SDRAM-Modules
Standby and Refresh Currents (Ta = 0 to 70 oC, VCC = 3.3V 0.3V) 1) Parameter Operating Current Symbol Icc1 Test Condition
Burst length = 4, CL=3 trc>=trc(min.), tck>=tck(min.), Io=0 mA 2 bank interleave operation CKE<=VIL(max), tck>=tck(min.) CKE<=VIL(max), tck=infinite CKE>=VIH(min), tck>=tck (min.), input changed once in 3 cycles CKE>=VIH(min), tck=infinite, no input change CKE<=VIL(max), tck>=tck(min.) CKE<=VIL(max), tck=infinite CKE>=VIH(min), tck>=tck (min.) input changed one time CKE=>VIH(min),tck=infinite, no input change
X64 800
X72 900 mA
Note
max. 1,2
Precharged Standby Current in Power Down Mode Precharged Standby Current in Nonpower Down Mode Active Standby Current in Power Down Mode Active Standby Current in Nonpower Down Mode Burst Operating Current
Icc2P Icc2PS Icc2N Icc2NS Icc3P Icc3PS Icc3N Icc3NS Icc4
24 16 160 80 24 16 200 120 760
27 18 180 90 27 18 225 135 855
mA mA mA CS= High mA mA mA mA CS= High mA mA 1,2
Burst length = full page, trc = infinite, CL = 3, tck>=tck (min.), Io = 0 mA 2 banks activated trc>=trc(min) CKE=<0,2V
Auto (CBR) Refresh Current Self Refresh Current
Icc5 Icc6
720 16
810 18
mA mA
1,2
1,2
Semiconductor Group
7
HYS64(72)V2200/4220GCU-10 SDRAM-Modules
AC Characteristics 3)4) TA = 0 to 70 C; VSS = 0 V; VCC = 3.3 V 0.3 V, tT = 1 ns Parameter
Symbol
Limit Values -10 min max
Unit Note
Clock and Clock Enable
Clock Cycle Time CAS Latency = 3 CAS Latency = 2 CAS Latency = 1 System Frequency CAS Latency = 3 CAS Latency = 2 CAS Latency = 1 Clock Access Time CAS Latency = 3 CAS Latency = 2 CAS Latency = 1 Clock High Pulse Width Clock Low Pulse Width CKE Setup Time CKE Hold Time CKE Setup Time (Power down mode) CKE Setup Time (Self Refresh Exit) Transition time (rise and fall)
tCK
10 15 30 ns ns ns 100 66 33 8 9 27 - - - - - - 30 MHz MHz MHz ns ns ns ns ns ns ns ns ns ns
6 6 6 8 5
fCK
- - -
tAC
- - -
tCH tCL tCKS tCKH tCKSP tCKSR tT
3.5 3.5 3 1 3 8 1
Common Parameters
Command Setup time Command Hold Time Address Setup Time Address Hold Time RAS to CAS delay Cycle Time Active Command Period Precharge Time Bank to Bank Delay Time
tCS tCH tAS tAH tRCD tRC tRAS tRP tRRD
3 1 3 1 30 75 45 30 20
- - - - -
120k 120k
ns ns ns ns ns ns ns ns ns
6 6 6 6
- -
Semiconductor Group
8
HYS64(72)V2200/4220GCU-10 SDRAM-Modules
Parameter
Symbol
Limit Values -10 min max 1 -
Unit Note
CAS to CAS delay time (same bank)
tCCD
CLK
Refresh Cycle
Self Refresh Exit Time Refresh Period (4096 cycles)
tSREX tREF
2Clk +tRC
- 64
ns ms
8 7
-
Read Cycle
Data Out Hold Time Data Out to Low Impedance Time
tOH tLZ
3 0 - - - 2
- - 6 8 25 -
ns ns
9
tHZ Data Out to High Impedance Time CAS Latency = 3 CAS Latency = 2 CAS Latency = 1
DQM Data Out Disable Latency
ns ns ns CLK
tDQZ
Write Cycle
Data In Setup Time Data In Hold Time Data input to Precharge Data In to Active/refresh DQM Write Mask Latency
tDS tDH tDPL tDAL tDQW
3 1
2 5
- - - - -
ns ns CLK CLK 10 CLK
0
Semiconductor Group
9
HYS64(72)V2200/4220GCU-10 SDRAM-Modules
Notes: 1. The specified values are valid when addresses are changed no more than once during tck(min.) and when No Operation commands are registered on every rising clock edge during tRC(min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ' are stable during tRC(min.). s) 3. All AC characteristics are shown for device level. An initial pause of 100s is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have V il = 0.4 V and V ih = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between V ih and Vil. All AC measurements assume t T=1ns with the AC output load circuit show. Specified tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V.
tCH 2.4 V CLOCK 0.4 V tCL tSETUP tHOLD
+ 1.4 V 50 Ohm Z=50 Ohm I/O 50 pF
tT
INPUT
1.4V
tAC tLZ tOH
tAC
I/O 50 pF
1.4V
OUTPUT
Measurement conditions for tac and toh
tHZ
5. 6. 7. 8.
fig.1 If clock rising time is longer than 1ns, a time (t T/2 -0.5) ns has to be added to this parameter. Rated at 1.5 V If tT is longen than 1 ns, a time (t T -1) ns has to be added to this parameter. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to " ake-up"the device. w 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 10.Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 11.tDAL is equivalent to t DPL + tRP.
Semiconductor Group
10
HYS64(72)V2200/4220GCU-10 SDRAM-Modules
A serial presence detect storage device - E 2PROM - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E 2PROM device during module production using a serial presence detect protocol ( I 2C synchronous 2-wire bus)
PD-Table:
Byte# Description SPD Entry Value Hex 2Mx64 2Mx72 4Mx64 4Mx72 -10 -10 -10 -10 80 80 80 80 08 08 08 08 04 04 04 04 0B 0B 0B 0B 09 09 09 09 01 40 00 01 A0 80 00 80 08 00 01 8F 02 07 01 01 00 06 F0 90 78 6C 1E 14 01 48 00 01 A0 80 02 80 08 08 01 8F 02 07 01 01 00 06 F0 90 78 6C 1E 14 02 40 00 01 A0 80 00 80 08 00 01 8F 02 07 01 01 00 06 F0 90 78 6C 1E 14 02 48 00 01 A0 80 02 80 08 08 01 8F 02 07 01 01 00 06 F0 90 78F 6C 1E 14
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses (for x8 SDRAM) Number of DIMM Banks Module Data Width Module Data Width (cont' d) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type SDRAM width, Primary Error Checking SDRAM data width Minimum clock delay for back-to-back random column address Burst Length supported Number of SDRAM banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM module attributes SDRAM Device Attributes :General Min. Clock Cycle Time at CAS Latency = 2 Max. data access time from Clock for CL=2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL=1 Minimum Row Precharge Time Minimum Row Active to Row Active delay tRRD
128 256 SDRAM 11 9 2 64 / 72 0 LVTTL 10.0 ns 8.0 ns none / ECC Self-Refresh, 15.6s x8 n/a / x8 tccd = 1 CLK 1, 2, 4, 8 & full page 2 CAS lat. = 1,2 & 3 CS latency = 0 Write latency = 0 non buffered/non reg. Vcc tol +/- 10% 15.0 ns 9.0 ns 30 ns 27 ns 30 ns 20 ns
Semiconductor Group
11
HYS64(72)V2200/4220GCU-10 SDRAM-Modules
SPD-Table (cont' ): d
Byte# Description SPD Entry Value Hex 2Mx64 2Mx72 4Mx64 4Mx72 1E 2D 04 30 10 30 10 FF 12 XX 100 MHz 64 AF FF 1E 2D 04 30 10 30 10 FF 12 XX 64 AF FF 1E 2D 04 30 10 30 10 FF 12 XX 64 FF FF 1E 2D 04 30 10 30 10 FF 12 XX 64 FF FF
29 30 31 32 33 34 35 36-61
Minimum RAS to CAS delay tRCD Minimum RAS pulse width tRAS Module Bank Density (per bank) SDRAM input setup time SDRAM input hold time SDRAM data input setup time SDRAM data input hold time Superset information (may be used in future) 62 SPD Revision 63 Checksum for bytes 0 - 62 64- Manufactures' information (optional) s 125 (FFh if not used) 126 Frequency Specification 127 Details of 100 MHz Support 128+ Unused storage locations
30 ns 45 ns 16 MByte 3 ns 1 ns 3 ns 1 ns
Revision 1.2
Semiconductor Group
12
HYS64(72)V2200/4220GCU-10 SDRAM-Modules
L-DIM-168-C2 SDRAM DIMM Module package
133,35
127,35
4,0
1
3,0
10
11 42,18 66,68
40
41
84
A
85 94 95
B
124 125
C
168
6,35
3,125 3,125
6,35
1,27 2,54 min.
1,0 + 0.5 -
2,0
2,0
Detail C
Detail A
Detail B
17,78
0,2+ 0,15 -
Semiconductor Group
13
25,40 DM168-C2.WMF

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